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april 2009 ? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 fan102 ? primary-side-control pwm controller fan102 primary-side-control pwm controller features ? constant-voltage (cv) and constant-current (cc) control without secondary-feedback circuitry ? green mode: frequency reduction at light load ? fixed pwm frequency at 42khz with frequency hopping to reduce emi ? cable voltage drop compensation in cv mode ? low startup current: 10 a ? low operating current: 3.5ma ? peak-current-mode control in cv mode ? cycle-by-cycle current limiting ? v dd over-voltage protection with auto-restart ? v dd under-voltage lockout (uvlo) ? gate output maximum voltage clamped at 18v ? fixed over-temperature protection with auto- restart ? sop-8 package available applications ? battery chargers for cellular phones, cordless phones, pda, digital cameras, power tools ? replaces linear transformer and rcc smps ? offline high brightness (hb) led drivers description the primary-side pwm controller significantly simplifies power supply design that requires cv and cc regulation capabilities. the fan102 controls the output voltage and current precisely with the information in the primary side of the power supply, not only removing the output current sensing loss, but eliminating all secondary feedback circuitry. the green-mode function with a low startup current (10a) maximizes the light-load efficiency so the power supply can meet stringent standby power regulations. compared with a conventional secondary-side regulation approach, the fan102 can reduce total cost, component count, size, and weight; while simultaneously increasing efficiency, productivity, and system reliability. a typical output cv/cc characteristic envelope is shown in figure 1. figure 1. typical output v-i characteristic ordering information part number operating temperature range eco status package packing method fan102my -40c to +105c green 8-lead, small outline package (sop-8) tape & reel for fairchild?s definition of eco status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html .
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 2 fan102 ? primary-side-control pwm controller application diagram n p n s r sn1 c sn1 v dl + - ac line d sn d r c o 1 n a c dd bridge rectifier diode v o c dl cs comr comi comv gate vdd sgnd vs r start r sn2 c sn2 8 7 6 5 2 3 4 fan102 i o r s1 r s2 c s r gate r cs r comv c comv r comi c comi r comr c comr d dd figure 2. typical application internal block diagram 7 + - 16v/5v internal bias vdd + - 2 s r q q 1 5 comr vs cs osc with frequency hopping 28v otp v dd good s r q q green mode controller + - 3 comi + - + - 1.3v leading-edge blanking t dis detector i o estimator v o estimator + - + - 2.5v ea_i cable drop compensation ea_v 4 comv soft-driver 8 gate v dd slope compensation protection reset pwm comparator pwm comparator pwm comparator 6 brownout protection gnd temperature compensation figure 3. functional block diagram
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 3 fan102 ? primary-side-control pwm controller marking information figure 4. top mark pin configuration figure 5. pin configuration pin definitions pin # name description 1 cs current sense . this pin connects a current-sense resistor to sense the mosfet current for peak-current-mode control in cv mode and provides for output-current regulation in cc mode. 2 comr cable compensation . this pin is connects a capacitor between comr and gnd for compensation voltage drop due to output cable loss in cv mode. 3 comi constant current loop compensation . this pin is connects a capacitor and a resistor between comi and gnd for compensation current loop gain. 4 comv constant voltage loop compensation . this pin is connects a capacitor and a resistor between comv and gnd for compensation voltage loop gain. 5 vs voltage sense . this pin detects the output voltage information and discharges time base on voltage of auxiliary winding. this pin connects two divider resistors and one capacitor. 6 gnd ground . 7 vdd power supply . ic operating current and mosfet driving current are supplied using this pin. this pin is connected to an external v dd capacitor (typically 10 f). the threshold voltages for startup and turn-off are 16v and 5v, respectively. 8 gate pwm signal output . this pin outputs pwm signal and includes the internal totem-pole output driver to drive the external power mosfet. the clamped gate output voltage is 18v. f - fairchild logo z- plant code x- 1-digit year code y- 1-digit week code tt- 2-digit die run code t- package type (m=sop) p- z: pb free, y: green package m- manufacture flow code
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 4 fan102 ? primary-side-control pwm controller absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd dc supply voltage (1,2) 30 v v vs vs pin input voltage -0.3 7.0 v v cs cs pin input voltage -0.3 7.0 v v comv voltage error amplifier output voltage -0.3 7.0 v v comi voltage error amplifier output voltage -0.3 7.0 v p d power dissipation (t a 50c) 660 mw ja thermal resistance (junction-to-air) 150 c /w jc thermal resistance (junction-to-case) 39 c /w t j operating junction temperature +150 c t stg storage temperature range -55 +150 c t l lead temperature (wave soldering or ir, 10 seconds) +260 c electrostatic discharge capability, human body model, jedec- jesd22_a114 4.5 kv esd electrostatic discharge capability, charged device model, jedec- jesd22_c101 1250 v notes: 1. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. 2. all voltage values, except differential voltages, are given with respect to gnd pin. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter conditions min. typ. max. unit t a operating ambient temperature -40 +105 c
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 5 fan102 ? primary-side-control pwm controller electrical characteristics v dd =15v and t a =25c unless otherwise specified. symbol parameter conditions min. typ. max. units v dd section v op continuously operating voltage 25 v v dd-on turn-on threshold voltage 15 16 17 v v dd-off turn-off threshold voltage 4.5 5.0 5.5 v i dd-op operating current v dd =20v, f s =f osc , v vs =2v, v cs =3v, c l =1nf 3.5 5.0 ma i dd-st startup current 0< v dd < v dd-on -0.16v 0 1.6 10.0 a i dd-green green-mode operating supply current v dd =20v, v vs =2.7v f s =f osc-n-min , v cs =0v c l =1nf, v comv =0v 1 2 ma v dd-ovp v dd over-voltage protection level v cs =3v, v vs =2.3v 27 28 29 v t d-vddovp v dd over-voltage protection debounce time f s =f osc , v vs =2.3v 100 250 400 s oscillator section center frequency t a =25c 39 42 45 f osc frequency frequency hopping range t a =25c 1.8 2.6 3.6 khz t fhr frequency hopping period t a =25c 3 ms f osc-n-min minimum frequency at no load v vs =2.7v, v comv =0v 550 hz f osc-cm-min minimum frequency at ccm v vs =2.3v, v cs =0.5v 20 khz f dv frequency variation vs. v dd deviation v dd =10v to 25v 5 % f dt frequency variation vs. temperature deviation t a =-40c to +105c 15 % voltage-sense section i vs-uvp sink current for brownout protection r vs =20k 180 a i tc ic compensation bias current 9.5 a v bias-comv adaptive bias voltage dominated by v comv v comv =0v, t a =25c, r vs =20k ? 1.4 v current-sense section t pd propagation delay to gate output 100 200 ns t min-n minimum on time at no load v vs =-0.8v, r s =2k ? , v comv =1v 1100 ns t mincc minimum on time in cc mode v vs =0v, v comv =2v 400 ns v th threshold voltage for current limit 1.3 v continued on the following page?
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 6 fan102 ? primary-side-control pwm controller electrical characteristics v dd =15v and t a =25c unless otherwise specified. symbol parameter conditions min. typ. max. units voltage-error-am plifier section v vr reference voltage 2.475 2.500 2.525 v v n green mode starting voltage on comv pin f s =f osc -2khz, v vs =2.3v 2.8 v v g green mode ending voltage on comv pin f s =1khz 0.8 v i v-sink output sink current v vs =3v, v comv =2.5v 90 a i v-source output source current v vs =2v, v comv =2.5v 90 a v v-hgh output high voltage v vs =2.3v 4.5 v current-error-amplifier section v ir reference voltage 2.475 2.500 2.525 v i i-sink output sink current v cs =3v, v comi =2.5v 55 a i i-source output source current v cs =0v, v comi =2.5v 55 a v i-hgh output high voltage v cs =0v 4.5 v cable compensation section v comr variation test voltage on comr pin for cable compensation r comr =100k ? 0.735 v gate section dcy max maximum duty cycle 75 % v ol output voltage low v dd =20v, i o =10ma 1.5 v v oh output voltage high v dd =8v, i o =1ma 5 v v oh_min output voltage high v dd =5.5v, i o =1ma 4 v t r rising time v dd =20v, c l =1nf 200 300 ns t f falling time v dd =20v, c l =1nf 80 150 ns v clamp output clamp voltage v dd =25v 15 18 v over-temperature-protection section t otp threshold temperature for otp (3) +140 c note: 3. when over-temperature protection is activated, the power system enters auto restart mode and output is disabled.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 7 fan102 ? primary-side-control pwm controller typical performance characteristics 14.6 15 15.4 15.8 16.2 16.6 17 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) v dd-on (v) 4.5 4.7 4.9 5.1 5.3 5.5 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) v dd-off (v) figure 6. turn-on threshold voltage (v dd-on ) vs. temperature figure 7. turn-off threshold voltage (v dd-off ) vs. temperature 2 2.4 2.8 3.2 3.6 4 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) i dd-op (ma) 35 37 39 41 43 45 47 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) f osc (khz) figure 8. operating current (i dd-op ) vs. temperature figure 9. center frequency (f osc ) vs. temperature 2.475 2.485 2.495 2.505 2.515 2.525 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) v vr (v) 2.475 2.485 2.495 2.505 2.515 2.525 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) v ir (v) figure 10. reference voltage (v vr ) vs. temperature figure 11. reference voltage (v ir ) vs. temperature
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 8 fan102 ? primary-side-control pwm controller typical performance characteristics 500 520 540 560 580 600 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) f osc-n-min (hz) 17 18 19 20 21 22 23 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) f osc-cm-min (khz) figure 12. minimum frequency at no load (f osc-n-min ) vs. temperature figure 13. minimum frequency at ccm (f osc-cm-min ) vs. temperature 0 5 10 15 20 25 30 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) s g (khz/v) 850 930 1010 1090 1170 1250 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) t min-n (ns) figure 14. green mode frequency decreasing rate (s g ) vs. temperature figure 15. minimum on time at no load (t min-n ) vs. temperature 0 0.5 1 1.5 2 2.5 3 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) v n (v) 0 0.2 0.4 0.6 0.8 1 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) v g (v) figure 16. green mode starting voltage on comv pin (v n ) vs. temperature figure 17. green mode ending voltage on comv pin (v g ) vs. temperature
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 9 fan102 ? primary-side-control pwm controller typical performance characteristics 80 83 86 89 92 95 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) i v-sink (a) 75 79 83 87 91 95 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) i v-source (a) figure 18. output sink current (i v-sink ) vs. temperature figure 19. output source current (i v-source ) vs. temperature 50 52 54 56 58 60 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) i i-sink (a) 50 52 54 56 58 60 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) i i-source (a) figure 20. output sink current (i i-sink ) vs. temperature figure 21. output source current (i i-source ) vs. temperature 0 0.4 0.8 1.2 1.6 2 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) v comr (v) 60 64 68 72 76 80 -40 -30 -15 0 25 50 75 85 100 125 temperature (oc) dcy max (%) figure 22. variation test voltage on comr pin for cable compensation (v comr ) vs. temperature figure 23. maximum duty cycle (dcy max ) vs. temperature
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 10 fan102 ? primary-side-control pwm controller functional description figure 24 shows the basic circuit diagram of primary- side regulated flyback converter with typical waveforms shown in figure 25. generally, discontinuous conduction mode (dcm) operation is preferred for primary-side regulation since it allows better output regulation. the operation principles of dcm flyback converter are as follows: during the mosfet on time (t on ), input voltage (v dl ) is applied across the primary-side inductor (l m ). then mosfet current (i ds ) increases linearly from zero to the peak value (i pk ). during this time, the energy is drawn from the input and stored in the inductor. when the mosfet is turned off, the energy stored in the inductor forces the rectifier diode (d) to turn on. while the diode is conducting, the output voltage (v o ), together with diode forward voltage drop (v f ), are applied across the secondary-side inductor ( l m n s 2 / n p 2 ) and the diode current (i d ) decreases linearly from the peak value (i pk n p /n s ) to zero. at the end of inductor current discharge time (t dis ), all the energy stored in the inductor has been delivered to the output. when the diode current reaches zero, the transformer auxiliary winding voltage (v w ) begins to oscillate by the resonance between the primary-side inductor (l m ) and the effective capacitor loaded across mosfet. during the inductor current discharge time, the sum of output voltage and diode forward voltage drop is reflected to the auxiliary winding side as (v o +v f ) n a /n s . since the diode forward voltage drop decreases as current decreases, the auxiliary winding voltage reflects the output voltage best at the end of diode conduction time where the diode current diminishes to zero. by sampling the winding voltage at the end of the diode conduction time, the output voltage information can be obtained. the internal error amplifier for output voltage regulation (ea_v) compares the sampled voltage with internal precise reference to generate error voltage (v comv ), which determines the duty cycle of the mosfet in cv mode. meanwhile, the output current can be estimated using the peak drain current and inductor current discharge time since output current is same as average of the diode current in steady state. the output current estimator picks up the peak value of the drain current with a peak detection circuit and calculates the output current using the inductor discharge time (t dis ) and switching period (t s ). the output information is compared with internal precise reference to generate error voltage (v comi ), which determines the duty cycle of the mosfet in cc mode. among the two error voltages, v comv and v comi , the smaller actually determines the duty cycle. during constant voltage regulation mode, v comv determines the duty cycle while v comi is saturated to high. during constant current regulation mode, v comi determines the duty cycle while v comv is saturated to high. + v dl - l m + v o - n p :n s i ds i d d primary-side regulation controller + v w - v dd gate v s cs +v f - n a l o a d i o i o estimator v o estimator t dis detector pwm control r cs v ac ref ref ea_v ea_i v comv v comi r s1 r s2 figure 24. simplified psr flyback converter circuit i ds (mosfet drain-to-source current) t dis t on t s i d (diode current) v w (auxiliary winding voltage) p pk s n i n ? pk i . davg o ii = a f s n v n ? a o s n v n ? figure 25. key waveforms of dcm flyback converter
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 11 fan102 ? primary-side-control pwm controller cable voltage drop compensation when it comes to cellular ph one charger applications, the actual battery is located at the end of cable, which causes typically several percent of voltage drop on the actual battery voltage. fan102 has a programmable cable voltage drop compensation, which provides a constant output voltage at the end of the cable over the entire load range in cv mode. as load increases, the voltage drop across the cable is compensated by increasing the reference voltage of voltage regulation error amplifier. the amount of compensation is programmed by the resistor on the comr pin. the relationship between the amount of compensation and comr resistor is shown in figure 26. 1 2 3 4 5 6 7 8 9 10 11 12 13 compensation percentage (%) 10 20 30 40 50 60 70 80 90 100 r comr (k ) 14 15 figure 26. cable voltage drop compensation temperature compensation built-in temperature compensation provides constant voltage regulation over a wide range of temperature variation. this internal compensation current compensates the forward-voltage drop variation of the secondary-side rectifier diode. green-mode operation the fan102 uses voltage regulation error amplifier output (v comv ) as an indicator of the output load and modulates the pwm frequency, as shown in figure 27, such that the switching frequency decreases as load decreases. in heavy load conditions, the switching frequency is fixed at 42khz. once v comv decreases below 2.8v, the pwm frequency starts to linearly decrease from 42khz to 550hz to reduce the switching losses. as v comv decreases below 0.8v, the switching frequency is fixed at 550hz and fan102 enters deep green mode, where the operating current reduces to 1ma, further reducing the standby power consumption. switching frequen cy 42khz 550h z v comv 2.8v 0.8v green mode normal mode deep green mode figure 27. switching frequency in green mode frequency hopping emi reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth measured by the emi test equipment. fan102 has an internal frequency hopping circuit that changes the switching frequency between 39.4khz and 44.6khz with a period of 3ms, as shown in figure 28. t s t s t s gate drive signal f s 3ms t 44.6khz 44.6khz 39.4khz 42.0khz figure 28. frequency hopping
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 12 fan102 ? primary-side-control pwm controller leading-edge blanking (leb) at the instant the mosfet is turned on, a high-current spike occurs through the mosfet, caused by primary- side capacitance and secondary-side rectifier reverse recovery. excessive voltage across the r cs resistor can lead to premature turn-off of mosfet. fan102 employs an internal leading-edge blanking (leb) circuit. to inhibit the pwm comparator for a short time after the mosfet is turned on. thus, external rc filtering is not required. startup figure 29 shows the typical startup circuit and transformer auxiliary winding for a fan102 application. before fan102 begins switching, it consumes only startup current (typically 10a) and the current supplied through the startup resistor charges the v dd capacitor (c dd ). when v dd reaches turn-on voltage of 16v (v dd- on ), fan102 begins switching and the current consumed by fan102 increases to 3.5ma. then, the power required for fan102 is supplied from the transformer auxiliary winding. the large hysteresis of v dd provides more holdup time, which allows using a small capacitor for v dd . np v dl + - ac line 1 n a c dd c dl cs comr comi comv gate vdd sgnd vs r star t 8 7 6 5 2 3 4 fan102 r s1 r s2 d dd figure 29. startup circuit protections the fan102 has several self-protective functions, such as over-voltage protection (ovp), over-temperature protection (otp) and brownout protection. all the protections are implemented as auto-restart mode. once the fault condition occurs, switching is terminated and the mosfet remains off. this causes v dd to fall. when v dd reaches the v dd turn-off voltage of 5v, the current consumed by fan102 reduces to the startup current (typically 10a) and the current supplied startup resistor charges the v dd capacitor. when v dd reaches the turn-on voltage of 16v, fan102 resumes normal operation. in this manner, the auto-restart alternately enables and disables the switching of the mosfet until the fault condition is eliminated ( see figure 30 ). fault situation 5v 16v v dd v ds fault occurs fault removed normal operation normal operation power on operating current 3.5ma 10a figure 30. auto-restart operation v dd over-voltage protection (ovp) v dd over-voltage protection prevents damage from over- voltage conditions. if the v dd voltage exceeds 28v by open feedback condition, ovp is triggered. the ovp has a de-bounce time (typcal 250s) to prevent false trigger by switching noise. it also protects other switching devices from over voltage. over-temperature protection (otp) a built-in temperature-sensing circuit shuts down pwm output if the junction temperature exceeds 140c. brownout protection fan102 detects the line voltage using auxiliary winding voltage since the auxiliary winding voltage reflects the input voltage when the mosfet is turned on. the vs pin is clamped at 1.15v while the mosfet is turned on and brownout protection is triggered if the current out of the vs pin is less than i vs-uvp (typical 180a) during the mosfet conduction. pulse-by-pulse current limit when the sensing voltage across the current sense resistor exceeds the internal threshold of 1.4v, the mosfet is turned off for the remainder of switching cycle. in normal operation, the pulse-by-pulse current limit is not triggered since the peak current is limited by the control loop.
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 13 fan102 ? primary-side-control pwm controller typical application circuit (primary-side regulated flyback charger) application fairchild devices input voltage range output cell phone charger fan102 90~265v ac 5v/0.78a (3.9w) features ? high efficiency (>68% at full load) meeting energy star sm v2.0 and cec regulation with enough margin ? low standby power consumption (pin=0.087w for 115v ac and pin=0.123w for 230v) ? tight output regulation (cv: 5%, cc: 7%) 62 64 66 68 70 72 74 25 50 75 100 load (%) efficiency (%) 115v60hz (70.7% avg) 230v50hz (68.3% avg) 62.2% : cec (2008) 66.3% : energy star v2.0 (nov. 2008) 0 1 2 3 4 5 6 0 100 200 300 400 500 600 700 800 900 output current (ma) output voltage (v) ac90v ac120v ac230v ac264v figure 31. measured efficiency and output regulation n1 n3 r sn1 c sn1 v dl + - ac line d sn d r c o 1 n2 c dd v o l p c p c dl1 cs comr comi comv gate vdd sgnd vs r start r sn2 c sn2 8 7 6 5 2 3 4 fan102 i o r s1 r s2 c s r gate r cs r comv c comv r comi c comi r comr c comr 100k ? 1nf 2m ? 1n4007 270 ? r damp 115k ? 24.9k ? 1.6 ? 100 ? 10f 47pf 4.7f 1n4007 1n4007 1n4007 1n4007 4.7f c dl2 1mh 1k ? 10nf 43k ? 68nf 200k ? 82k ? 1f 1nf 30 ? 470f 220f 1k ? r pl 15h sb260 1n4007 d dd q mo s fe t fqu1n60c figure 32. schematic of typical application circuit
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 14 fan102 ? primary-side-control pwm controller typical application circuit (continued) transformer specification ? core: ee16 ? bobbin: ee16 pin specification remark primary-side inductance 1 3 2.3mh 5% 100khz, 1v primary-side effective leakage 1 8 65 h 5%. short one of the secondary windings
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 15 fan102 ? primary-side-control pwm controller physical dimensions 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m ba 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge figure 33. 8-lead, small outline package (sop-8) package drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2008 fairchild semiconductor corporation www.fairchildsemi.com fan102 rev. 1.0.3 16 fan102 ? primary-side-control pwm controller

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